Capability and Design Guidelines
Current Technology
| Maximum number of layers: | 36 |
|---|---|
| Minimum track: | 75µm (3 mil) |
| Minimum gap: | 75µm (3 mil) |
| Smallest mechanically drilled holes: | 150µm (6 mil) |
| Smallest mechanically drilled blind holes: | 150µm (6 mil) |
| Smallest laser drilled holes: | 25µm (1 mil) |
| Smallest laser drilled blind holes: | 50µm (2 mil) |
| Smallest buried holes: | 25µm (1 mil) |
| Aspect ratio max - through holes: | 16 : 1 (FHS) |
| Aspect ratio max - blind holes: | 1 : 1 (FHS) |
| Drilled hole edge to copper (M/L rigids): | 175µm (7 mil) |
| Drilled hole edge to copper (F/Rs): | 225µm (9 mil) |
| Controlled Impedance <Read More> | +/- 10% |
| Vias in S/M pads | |
| Planar transformers | |
| Chip on-board and component in-board | |
| Edge plating | |
| Edge plated half holes | |
| Edge plated fingers | |
| Buried resistors | +/- 3% |
| Solder resist laser ablation | |
| Resin filled vias | |
| Laser structuring (copper pattern and solder resist) | |
| Copper filled blind vias |